The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to device structures for field-effect transistors, as well as methods of fabricating a device structure for a field-effect transistor.
Common transistor structures include a source, a drain, a channel situated between the source and drain, and a gate electrode configured to respond to a gate voltage by selectively connecting the source and drain to each another through the channel. Nanotechnology may represent a candidate technology that can be used to meet scaling requirements. In particular, semiconductor nanostructures, such as nanowires and nanosheets, may be attractive building blocks for the fabrication of field effect transistors. However, nanostructures may have exhibit problems with access resistance because of the limited volume of semiconductor material that is available for contacting the source/drain regions with metal contacts. The dopant in the semiconductor material of the source/drain regions may also exhibit a limited electrical activation level adjacent to the channel and to the metal contact, which can result in an elevated contact resistance.